(1) Field of the Invention
This invention relates to a CMOS pixel comprising an N− well formed in a P− epitaxial silicon layer with a dual gate PMOS transistors formed in the N− well.
(2) Description of the Related Art
U.S. Pat. No. 6,147,362 to Keyser describes a high performance pixel for active matrix electronic displays. The pixel combines a compact mesa-isolated PMOS access transistor with a novel, area efficient high voltage device.
U.S. Pat. No. 6,127,697 to Guidash describes an active pixel sensor comprising a substrate of a first conductivity type having a surface containing PMOS and NMOS implants that are indicative of a sub-micron CMOS process, a photodetector formed at a first depth from an implant of a second conductivity type that is opposite the first conductivity type on the surface, and a gate on the surface adjacent to the photodetector. The photodetector is formed by an implant of the second conductivity type that is deeper and more lightly doped than implants used within the sub-micron CMOS process.
U.S. Pat. No. 5,923,369 to Merrill et al. describes an active pixel sensor cell array in which a differential amplifier amplifies the output of each cell. The output of the differential amplifier is fed back to one of its inputs. The use of the differential amplifiers reduces fixed pattern noise in the image data generated by reading the array.
U.S. Pat. No. 5,917,547 to Merrill et al. describes an active pixel sensor array in which a two stage amplifier amplifies the output of each cell. The two stage amplifier design reduces fixed pattern noise in the image data generated by reading the array.